1. Field of the Invention
The present invention relates generally to the manufacture and processing of integrated circuit devices. Specifically, the present invention relates to an in-tray burn-in board and method of use for performing burn-in and electrical testing of a plurality of integrated circuit devices disposed in processing trays.
2. State of the Art
During the manufacture of integrated circuit (IC) devices, processing trays—also referred to as component trays, in-process trays, or carrier trays—are typically used throughout many phases of production for handling IC devices. Processing trays may be configured for use with a number of different types of packaged IC devices, including dual in-line packages (DIPs), zigzag in-line packages (ZIPs), thin small outline packages (TSOPs), small outline J-lead packages (SOJs), ball-grid arrays (BGAs), pin-grid arrays (PGAs), quad flat packages (QFPs), pad array carriers (PACs), and plastic leaded chip carriers (PLCCs). Processing trays may also be designed for handling bare, or unpackaged, semiconductor dice. The configuration of processing trays varies depending on the type of IC device that a particular tray is designed for use with and, also, on the function that tray is designed to perform.
Processing trays may be configured for transporting IC devices between various manufacturing work stations where a specific production step, such as, for example, burn-in testing, may be conducted. Processing trays may also be configured for the storing and shipping of IC devices. Trays used for shipping IC devices are often custom designed for a specific customer—generally referred to as customer trays—depending on the needs of that customer. U.S. Pat. No. 5,492,223 to Boardman et al., U.S. Pat. No. 5,203,452 to Small et al., U.S. Pat. No. 5,927,503 to Nevill et al., U.S. Pat. No. 5,103,976 to Murphy, and U.S. Pat. No. 5,636,745 to Crisp et al. disclose processing trays that may be used for processing, handling, shipping, or storage, or a combination thereof, of IC devices. These conventional trays generally include a frame enclosing a planar, open lattice structure. The latticework forms a two-dimensional array of cells, each cell being adapted to receive an individual IC device.
Another conventional processing tray design widely used within the semiconductor industry for handling IC devices during production is the JEDEC tray. These trays are designed and built in compliance with standards propagated by the Joint Electronic Device Engineering Counsel (JEDEC). Generally, a JEDEC tray includes a grid-like, open lattice structure that forms a planar, two-dimensional array of IC cells. Each IC cell is adapted to hold a single IC device. JEDEC trays are usually injection molded from plastic and vary in overall dimensions and grid size depending on the type of IC device the tray is designed to hold. JEDEC trays are stackable and also have surface features, such as locating and hold-down tabs, that facilitate manipulation of the trays by automatic processing and testing equipment.
Another device used for handling IC devices is a burn-in board. A burn-in board is a type of IC device carrier specifically designed for holding a plurality of IC devices during burn-in and electrical testing. Burn-in is a procedure directed to the detection of IC devices likely to fail during the first few hours of operation, prior to the installation of those IC devices in higher-level packaging for eventual inclusion in electronic equipment. Burn-in testing of IC devices typically comprises the application of specified electrical biases and signals in a controlled temperature environment. The characteristics, such as voltage and frequency, of the specified electrical biases and signals may be configured so as to subject the IC devices to a test environment more severe than the electrical environment the IC devices will likely experience during normal operation. Other environmental variables, such as, for example, humidity, may also be controlled during burn-in testing.
During a typical burn-in test, a plurality of IC devices is mounted on one or more burn-in boards, which are then placed in a test chamber having a controllable environment. Specified electrical biases and signals are applied to the IC devices while also subjecting the IC devices to thermal cycling, in which the temperature inside the test chamber is cycled between an elevated temperature—a temperature in excess of the ambient operating temperature the IC devices will likely experience during normal operation—and a below-ambient temperature—a temperature lower than the ambient operating temperature the IC device will likely experience during normal operation. Thermal cycling may include multiple temperature cycles, as well as extended testing at a specific temperature such as, for example, an elevated temperature. Applying electrical biases to the IC devices during thermal cycling accelerates the stress to which the IC devices are subjected to during burn-in. Therefore, marginal devices that might otherwise fail sometime after being placed in service are caused to fail during burn-in and are thus eliminated before shipment to customers or assembly into electronic equipment.
Electrical testing is a procedure used to verify that IC devices function according to their minimum rated specifications and to classify IC devices based on their operating characteristics. In electrical testing, a more complete set of operating electrical signals is supplied to the IC devices to provide a thorough evaluation of their functions. After electrical testing, the IC devices may be sorted,—based on an IC device's electrical characteristics exhibited under test,—into categories, or “bins,” according to a predetermined set of performance characteristics.
Conventional burn-in boards, which are commonly fabricated as printed circuit boards, exist in a wide variety of configurations. For example, U.S. Pat. No. 5,093,982 to Gussman, U.S. Pat. No. 5,329,093 to Okano, U.S. Pat. No. 4,684,182 to Gussman, and U.S. Pat. No. 5,247,248 to Fukunaga disclose burn-in boards for testing a plurality of IC devices. In addition, U.S. Pat. No. 5,517,125 to Posedel et al., U.S. Pat. No. 5,888,837 to Fillion et al., U.S. Pat. No. 5,367,253 to Wood et al., and U.S. Pat. No. 5,149,662 to Eichelberger disclose carrier trays specifically adapted for burn-in of a plurality of bare semiconductor dice. Also, U.S. Pat. No. 4,779,047 to Solstad et al. discloses a burn-in board configured for use with IC devices mounted on a carrier tape.
During the manufacture of IC devices, considerable time, labor, and cost are expended in handling IC devices throughout the many phases of production. For example, a plurality of IC devices may be disposed on a first processing tray for storage during production and for transportation within the manufacturing facility. That plurality of IC devices may then be unloaded from the first processing tray and disposed on a burn-in board for burn-in and electrical testing. Upon completion of burn-in and electrical testing, the plurality of IC devices may be sorted according to performance characteristics observed during burn-in and electrical testing. The sorted IC devices may again be placed on processing trays for handling and transportation within the manufacturing facility.
As evidence of the high costs to IC device manufacturers resulting from the handling of IC devices during production, much effort has been devoted to developing automated equipment specifically directed to the loading and unloading of IC devices for burn-in and electrical testing. For example, U.S. Pat. No. 5,307,011 to Tani, U.S. Pat. No. 4,660,282 to Pfaff, U.S. Pat. No. 5,267,395 to Jones, Jr. et al., U.S. Pat. No. 5,509,193 to Nuxoll, U.S. Pat. No. 5,842,272 to Nuxoll, and U.S. Pat. No. 4,817,273 to Lape et al. disclose apparatus for loading IC devices onto burn-in boards and for subsequent unloading of the IC devices onto processing trays or other transport media such as, for example, carrier tubes.
It is a continuing goal of the semiconductor industry to decrease the costs of fabricating IC devices while maintaining, or even improving, device integrity, performance and operating capabilities. One approach to achieving a reduction in manufacturing costs for IC devices is to reduce the costs associated with handling the IC devices throughout the manufacturing facility and all phases of production. Therefore, a need exists in the semiconductor industry for methods and devices directed toward reducing the time and cost associated with handling IC devices during production. Specifically, a need exists in the semiconductor industry for an apparatus and method of performing burn-in and electrical testing in situ on processing trays, thereby eliminating the need to load and subsequently unload IC devices between processing trays and burn-in boards.